Samsung’s Texas Chip Factory: A Pellicle-Driven Gamble to Outpace TSMC

Samsung’s Texas chip factory is about to rewrite the rules of semiconductor manufacturing—by finally embracing a technology it once dismissed as too costly.

The Taylor, Texas facility will achieve 'first light' with ASML EUV systems in March 2025, with risk production slated for year-end. Targeting 50,000 wafer starts per month using SF2/SF3P process technology, it will be Samsung’s largest logic fab.

A $44 billion campus includes two advanced fab modules, an advanced packaging facility, and an R&D center.

The facility will be the first Samsung fab to adopt EUV pellicles for patterning, with FST supplying $17.5 million in pellicle-handling systems. Pellicles address stochastic mask defects at 2nm+ nodes, improving yield stability for large dies like Tesla’s AI5 chips.

This shift contrasts with Samsung’s prior pellicle-free EUV strategy, which prioritized throughput over defect control.

Tesla’s AI6/AI5 chip contracts (2024–2033) resolved volume and customer uncertainty, accelerating equipment installation.

The decision to adopt pellicles reflects a strategic pivot toward yield stability for large dies, contrasting with TSMC’s pellicle-free approach and Intel’s 40,000 WSPM benchmark.